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power management 1 sc560 dua l output l ow noi se ldo linear regula tor ? 2014 sem tec h corporation fea tures inp ut voltage range 2.5v to 5.5v out put voltage ranges 1.2v to 5.0v (each ldo) max imum output current 300ma (both ldos) dropout at 200ma load 200mv max. qui escent supply cur ren t 10 0a (both ldos enabled) shutdown current 100na (typ) out put noise < 50v rms (sc560a and xe d output ver sions) psrr < -65db at 1khz (sc560a and xe d output ver sions) ove r-t emperature protection short -ci rcu it protection under- vol tage lockout pow er good monitor for output a (sc560c and xe d output versions) ind ependent enable/disable for ldob (SC560B and x ed output versions) mlpq-ut8, 1.5mm x 1.5mm x 0.6mm package lea d-free and halogen-free appl ications pdas and cellular phones gps devices pal mto p computers and handheld instruments tft/lcd applications wir eless handsets digital cordless phones and pcs phones per sonal communic ato rs wir eless lan nn n n n n n n n n n n n n n n n n n n n n n description the sc 560 is a family of dual output, ultra-low dropout linear voltage regulators designed for use in b att ery powered wireless applications. the sc 560a, SC560B, and sc560c pr ovi de adjustable output voltages that can be set using t wo ext ernal res istors. fixed output voltages are also a vai lable (see ordering information for av ailable com binations). fix ed output devices pr ovi de the po wer - good monitor, independent enable pins, and a bypass pin for low-noise operation all members of the sc560 family require an input voltage level between 2.5v and 5.5v. output voltages for the adjustable versions can vary between 1.2v and 5.0v. fixed output voltage options are also chosen from this range. the sc 560a pr ovi des superior lo w-n oise per for mance by using an e xte rna l bypass capacitor connected to pin 7 to lt er the bandgap reference. the SC560B uses pin 7 as a separ ate en able pin for the second regulator output so the t wo outputs can be controlled independe ntl y. the sc 560c uses this pin to pr ovi de a pgood output to hold a processor in reset when the voltage on outa is not in regulation. all other versions pr ovi de all three functions with xe d output voltages (no feedback pins are provided). the de vic e a lso pr ovi des pr ote cti on cir cui try su ch as cur ren t l imi tin g, und er- vol tag e l ock out , a nd the rma l pro tec tio n to p rev ent de vic e f ail ure s. sta bil ity is mai nta ine d b y u sin g 1 f capa cit ors on th e o utp ut pin s. the ml pq- ut8 pa cka ge and 04 02 cer ami c c apa cit ors minimi ze the re quire d pcb ar ea. c in 2 .2 f out a out b vin enb en out b en out a gnd enb pgo od b yp vin sc 560 d c out a 1 f c out b 1 f c byp 22 n f pgo od typ ical application circuit rev . 7.1
sc560 2 pin con gu rat ion mar kin g information ord ering information device pac kag e sc560xultrt (1)(2)(3) mlpq-ut8 1.51.5 sc560xevb (3) eva luation board notes: (1) a vai lable in tape and reel only. a reel contains 3,000 devices. (2) a vai lable in lead-free package only. device is weee and rohs com pliant and halogen-free. (3) the device variant is denoted by the x. 12 3 4 5 6 7 8 top vie w 0 n yw pin out and vol tage options device pin options out put v oltage opt ions par t no. cod e pin 4 pin 7 pin 8 v ldoa v ldob sc560a fba byp fbb adj adj 0a SC560B fba enb fbb adj adj 0b sc560c fba pgood fbb adj adj 0c sc560d enb byp pgood 2.8v 1.8v 0d sc560e enb byp pgood 2.85v 2.85v 0k sc560f enb byp pgood 2.5v 1.8v 0l sc560g enb byp pgood 2.8v 1.5v 0u sc560h enb byp pgood 3.3v 3.3v 0s sc560l enb byp pgood 3.3v 1.8v 0z mlpq-ut-8; 1.5x1.5, 8 lead ja = 157c/w 0n = part no. code see pin out and vol tage options tab le for details yw = datecode
sc560 3 exceeding the above speci cations may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical charac ter istics section is not recommended. notes: (1) tested ac cor ding to jedec standard jesd22-a114-b. (2) cal culated from package in still air, moun ted to 3 x 4.5 (in), 4 la yer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. abs olute maximum ratings vin (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0 .3 to +6.5 en, enb (v) . . . . . . . . . . . . . . . . . . . . . . . . . -0 .3 to (v in + 0 .3) pgood (v) . . . . . . . . . . . . . . . . . . . . . . . . . -0 .3 to (v in + 0 .3) pin vo ltage all other pins ( v) . . . . . . . . . -0 .3 to (v in + 0.3) outa, outb short circuit duration . . . . . . . . con tinuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended o per ati ng conditions amb ient tem perature range (c) . . . . . . . . . -4 0 < t a < +8 5 v in (v) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 5 < v in < 5. 5 v outa , v outb (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 2 < v out < 5. 0 the rmal information the rma l resistanc e, junction to ambient (2) (c/w) . . . 157 max imum junction tem perature (c) . . . . . . . . . . . . . . +150 sto rag e temperature range (c) . . . . . . . . . . . . -6 5 to +150 pea k ir reflow tem perature (10s to 30s) (c) . . . . . . . +260 unless otherwise noted v in = 3.6v, c in = 2.2f, c outa = c outb = 1f, v en = v enb = v in , t a = -40 to +85c. typ ical values are at t a = 25c. all speci cations apply to both ldos unless otherwise noted. par ameter sym bol con ditions min typ max units inp ut supply vol tage range v in 2.5 5.5 v out put voltage v outx v in > v outx + 0.3v 1.2 5.0 v out put voltage accuracy v outx v in = 2.5v to 5.5v, i outx = 0 to 300ma, v in > voutx + 0.3v -3 3 % max imum output current i max 300 ma dropout vol tage (1) v d i outx = 200ma, v outx = 2.5v 180 215 mv i outx = 200ma, v outx = 3.3v to 5.0v 100 mv shutdown cur ren t i sd t a = 25c 0.1 1 a qui escent cur ren t i q i outa = i outb = 0ma, t a = 25c 100 a loa d regulation v loa d i outx = 1ma to i max 20 mv line regulation v line i outx = 1ma -6 6 mv feed back regulation voltage (2) v fb 0.985 1 1.015 v cur ren t limit i lim 350 850 ma ele ctr ical charac ter istics
sc560 4 par ameter sym bol con ditions min typ max units noise (3) e n v in = 3.7v, i outx = 50ma , 10hz < f < 100khz, c byp = 22nf 50 v rms v in = 3.7v, i outx = 50ma , 10hz < f < 100khz 300 v rms pow er supply rejection rat io (3) psrr v in = 3.7v, i outx = 50ma, f = 1khz, c byp = 22nf 65 db v in = 3.7v, i outx = 50ma, f = 1khz 40 pgood delay (4) t delay 160 200 240 ms pgood threshold (4) v th-pgood per cen tage of nominal output, v outa falling 82 87 92 % sta rt- up time t su fro m off to 87% v outx , i outx = 50ma, c byp = 22nf (2) 1 ms pow er up delay bet ween ldoa and ldob (5) t delay del ay between v outa and v outb start-ups 128 s under voltage lockout v uvlo v in rising 2.15 2.25 2.35 v uvlo h yste res is v uvlo-hys 100 mv ove r temperature p rot ection thr eshold t ot tem perature rising 160 c ove r temperature h yste res is t ot- hys 20 c dig ital inputs log ic input high threshold v ih v in = 5.5v 1.25 v log ic input l ow thr eshold v il v in = 2.5v 0.4 v log ic input high cur ren t i ih v in = 5.5v 1 a log ic input l ow cur ren t i il v in = 5.5v 1 a dig ital outputs pgood output voltage l ow v ol i sink = 500a,v in =3.7v 7 20 mv ele ctr ical charac ter istics (continued) notes: (1) dropout voltage is de ne d as v in - v outx , when v outx is 100mv below the value of v outx at v in = v outx + 0.5v. (2) sc560a, SC560B and sc560c only (3) ex cep t SC560B and xed output versions (4) ex cep t sc560a and SC560B (5) sc560a and sc560c only
sc560 5 typ ical charac ter istics loa d regulation ldoa 0 1 2 3 4 5 6 0 50 100 150 200 250 out put cur ren t ( ma ) output voltage variation (mv) v out a = 3 .3 v , v in = 3 .6 v t a = 85 c t a = 25 c t a = - 40 c line regulation ldoa -0 .5 0 0 .5 1 1 .5 2 3 .3 3 .5 3 .7 3 .9 4 .1 4 .3 4 .5 4 .7 4 .9 5 .1 5 .3 5 .5 inp ut vol tag e (v) output voltage variation (mv) v out a = 3 .3 v , i out a = 1 ma t a = 85 c t a = 25 c t a = - 40 c line regulation ldob -0 .5 0 0 .5 1 1 .5 2 2 .5 3 2 .9 3 .1 3 .3 3 .5 3 .7 3 .9 4 .1 4 .3 4 .5 4 .7 4 .9 5 .1 5 .3 5 .5 inp ut vol tag e (v) output voltage variation (mv) v out b = 2 .8 v , i out b = 1 ma t a = 25 c t a = - 40 c t a = 85 c dro pout v oltage ldob 0 50 100 150 200 250 300 350 400 2 .5 2 . 55 2 .6 2 . 65 2 .7 2 . 75 2 .8 2 . 85 2 .9 2 . 95 3 3 . 05 3 .1 inp ut vol tag e (v) vin - vout (mv) v out b = 2 .8 v , i out b = 200 ma t a = 85 c t a = 25 c t a = - 40 c dro pout v oltage ldoa 0 50 100 150 200 250 300 2 . 95 3 3 . 05 3 .1 3 . 15 3 .2 3 . 25 3 .3 3 . 35 3 .4 3 . 45 3 .5 3 . 55 3 .6 inp ut vol tag e (v) vin - vout (mv) v out a = 3 .3 v , i out a = 200 ma t a = 85 c t a = - 40 c t a = 25 c loa d regulation ldob 0 1 2 3 4 5 6 7 8 0 50 100 150 200 250 out put cur ren t ( ma ) output voltage variation (mv) v out b = 2 .8 v , v in = 3 .6 v t a = 85 c t a = 25 c t a = - 40 c
sc560 6 typ ical charac ter istics (continued) psrr vs. frequency (both ldos) - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 100 1000 10000 frequenc y ( hz ) psrr (db) v out = 2 .8 v , i o = 50 ma , no c byp out put noise vs. load current (both ldos) 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 out put cur ren t ( ma ) output voltage noise (v) t = 85 c t = 25 c t = - 40 c v out = 2 .8 v , v in = 3 .7 v , c byp = 22nf psrr vs. frequency (both ldos) - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 100 1000 10000 frequenc y ( hz ) psrr (db) v out = 2 .8 v , i o = 50 ma , c byp = 22nf out put noise vs. load current (both ldos) 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 out put cur ren t ( ma ) v out = 2 .8 v , v in = 3 .7 v , no c byp t a = 85 c t a = 25 c t a = - 40 c output voltage noise (v) loa d t ran sient response ris ing edge (both ldos) v in = 3.6v, v out = 2.8v i out =10ma to 200ma (100ma/div) v out (10mv/div) loa d t ran sient response fal ling edge (both ldos) v in = 3.6v, v out = 2.8v i out =10ma to 200ma (100ma/div)) v out (10mv/div) 2 s /div 20 s /div
sc560 7 pin con gu rat ions and descriptions pin # pin name pin function sc560a SC560B sc560c sc560 fix ed output 1 1 1 1 outb out put for ldob 2 2 2 2 vin inp ut supply voltage terminal 3 3 3 3 outa out put for ldoa 4 4 4 fba feed back sense pin for ldoa connect this pin to an ext ernal resistor divider to set v outa 5 5 5 5 gnd ana log and digital ground 6 6 6 6 en log ic input active high enables both ldos for the sc560a and sc560c, or ldoa for all other variants. en must be active in the SC560B and the xed output variants before enb can be activa ted . 7 7 byp ldo bypass output bypass with a 22nf capacitor 7 4 enb log ic input active high enables ldob for SC560B and the xed vol tage variants. 7 8 pgood pow er good output monitors the level of ldoa, switches low when the output drops out of regulation (pgood is open drain). 8 8 8 fbb feed back sense pin for ldob connect this pin to an ex ter nal res istor divider to set v outb typ ical charac ter istics (continued) sc560a noise spectrum 1 10 100 1000 10000 0. 01 0 .1 1 10 100 1000 frequenc y (khz) noise (nv/rthz) v in = 5v, fb = 10k//0.1f+5k, by pass=22nf, c out =1f sc560a psrr vs. frequency (both ldos) 0 10 20 30 40 50 60 70 80 90 0 .1 1 10 100 1000 10000 fre quenc y (khz) psrr (db) v in = 5v, fb = 10k//0.1f+5k, load=10ma, by pass=22nf, c out =10f
sc560 8 block diagrams vref uvl o o /t pow er - on logic ldo b ldo a 1 2 3 6 5 8 7 4 en gnd vin enb out a out b fbb fba sc 560 b vin vin vin vref uvl o o /t pow er - on logic ldo b ldo a 1 2 3 6 5 8 7 4 en gnd vin byp out a out b fbb vin vin vin fba sc 560 a
sc560 9 block diagrams (continued) vref uvl o o /t pow er - on logic ldo b ldo a 1 2 3 6 5 7 8 4 en gnd vin pgo od out a out b byp enb sc 560 C fix ed out put ver sio ns pgo od logic vin vin vin vref uvl o o /t pow er - on logic ldo b ldo a 1 2 3 6 5 8 7 4 en gnd vin pgo od out a out b fbb fba sc 560 c pgo od logic vin vin vin
sc560 10 detailed applic ati on circuits sc560a and SC560B out b en out a gnd fba fbb b yp vin sc 560 a c 1 22 nf 5 6 2 1 3 7 8 4 r 5 en r 6 vin c 4 2.2 f r 4 r 3 out a out b c 2 1 f c 3 1 f r 2 r 1 out b ena out a gnd enb pgo od byp vin sc 560 b 5 6 2 1 3 7 8 4 ena vin c 3 2.2 f out a out b c 2 1 f c3 1 f enb pgo od c 1 22nf v cc
sc560 11 detailed applic ati on circuits sc560c and sc560 fixed output ver sions out b en out a gnd fba fbb pgo od vin sc 560 c 5 6 2 1 3 7 8 4 en vin c4 2.2 f r 5 r4 out a out b c 2 1 f c 3 1 f r 2 r1 pgo od v cc out b ena out a gnd enb pgo od byp vin sc 560 (1) 5 6 2 1 3 7 8 4 ena vin c 4 2.2 f out a out b c 2 1 f c3 1 f not e : (1 ) sc 560 d t hrough sc 560 l c 1 22nf pgo od enb v cc
sc560 12 gen eral description the s c 560 is a family of dual output linear regulator devices intended for applications where low dropout voltage, low supply cur ren t, and low output noise are critical. each device provides a very simple, low cos t solution for t wo separa te reg ulated outputs. very little pcb area is required due to the miniature package size and the need for only fou r ex ter nal capacitors. the li near regulators ldoa and ldob are po wered fr om a single input supply rail, and each pr ovi des 300ma of output cur ren t. the sc 560 can pr ovi de output voltages in the range 1.2v to 5.0v. the ou tput voltages for the sc560a, SC560B and sc560c are set by connecting ext ernal res istor dividers to the feedback pins of each ldo. al l other versions of the sc560 ha ve x ed output vol tage values shown in the pinout and vol tage options table on page 2. ref er to the previous t wo pages for detailed application circuits for each version. pow er on control the sc 560a and sc560c devices ha ve a single enable pin (en) that controls both ldo outputs. pulling this pin low causes the device to en ter a l ow power shutdown mode where it typically dra ws 100na from the input supply. whe n en transitions high, the output of ldoa is enabled. aft er a delay of 128s, the output of ldob is enabled. in the sc560c, when the output voltage of ldoa reaches 87% of its regulation point, the delay timer starts and the pgood signal transitions high af ter a d elay of 200ms. the power up/down sequence is shown in the timing diag ram in figure 1. out a pgo od en out b 87 % 87 % 200 ms 128 s fig ure 1 tim ing diag ram the sc 560b and the xe d output variants pr ovi de a separa te enable pin for ldob which allo ws ldoa and ldob to be enabled independently. the en pi n controls the ldoa output and the enb pr ovi des the same functionality relative to the ldob output. the table shown below lists the e ec t of the polarity of the en and enb signals on the outputs of ldoa and ldob. note from the table that ldob can only be enabled when ldoa is already activ e. since ldob can be enabled separa tel y, there is no timing relationship between the t wo outputs at startup. en enb ldoa ldob low low o o low hig h o o hig h low on o hig h hig h on on the sc 560c and the xe d output variants ha ve a pgood signal which monitors the output of ldoa and transitions high 200ms af ter ld oa has reached 87% of its regulation point. this can be used to hold a processor in reset when the output voltage is out of regulation. note that when ldoa drops out of regulation and pgood is forced lo w, ldob is also disabled until pgood is reset. out put v oltage selection the ou tput voltage of each ldo for the sc560a, SC560B, and sc560c version is set independently using e xte rna l res istor dividers. fig ure 2 illustr ate s the proper connection for ldoa. out a fba r 1 r 2 fig ure 2 o utput v oltage feedback circuit appl ications information
sc560 13 appl ications information (continued) the va lues of the resistors in the voltage divider net wor k can be calcula ted using the equation: 2 2 1 ref out r r r v v where v ref = 1 v. th e value of r2 should be 100k? or less to ensure noise per for mance and stabilit y. val ues signi ca ntl y less than 100k? will impact the quiescent current. pro tec tion features the sc 560 family pr ovi des the following protection fea tures to ensure that no damage is incur red in th e event of a fault condition: under- vol tage lockout ove r-t emperature p rot ection short -ci rcu it protection under-voltage lockout the un der- vol tage lockout (uvl o) circuit protects the device from operating in an unknown state if the input vol tage supply is too lo w. whe n the v in dr ops below the uvlo threshold, the ldos are disabled and pgood is held low (sc560c and xe d output variants only). whe n v in is in creased above the hys ter esis level, the ldos are r e-e nabled in to their previous states, provided en has remained high. whe n powering up with v in be low the uvlo threshold, the ldos remain disabled and pgood is held low (sc560c and xed output variants only). ove r-temper ature pro tec tion an internal ove r-t emperature (ot ) protection circuit is provided that monitors the in ter nal junction temperature. whe n the temperature exc eeds the ot threshold as de ned in the electrical charac ter istics section, the ot protection disables both ldo outputs and holds the pgood signal lo w. whe n the junction temperature drops below the h yste res is level, the ldos are r e-e nabled in to their previous sta tes an d pgood transitions high af ter a 200ms dela y, provided en has remained high (sc560c and xed output variants only). ?? ? sho rt- cir cuit protection each output has shor t-c ircuit protection. if the output current exc eeds the cur ren t limit, the output voltage will drop and the output cur ren t will be limited until the load current ret urns to a speci ed le vel. if a s hort -ci rcu it occurs on the output of ldoa, the output of ldob will also be disabled until the fault is removed and the load current ret urns to a speci ed level. com pon ent selection a capacitance of 1f or larger on each output is rec ommended to ensure stabilit y. cer amic capacitors of type x5r or x7r should be used because of their low esr and stable temperature coe c ients. it is also rec ommended that the input be bypassed with a 2.2f, low esr x5r or x7r capacitor to minimize noise and impro ve transient response. note: tantalum and y5v capacitors are not recommended. the by p pin on the sc560d and the xe d output versions must ha ve a minimum of 22nf connected to g rou nd to meet all noise-sensitive req uirements. inc rea sing the capacitance to 100nf will further impr ove ps rr and output noise.
sc560 14 the rma l consider ati ons alt hough each of the t wo ldos in the sc560 can pr ovi de 300ma of output cur ren t, the maximum po wer di ssipation in the device is restric ted by th e miniature package size. the gr aphs in figure 3 and figure 4 can be used as a guideline to determine whether the input voltage, output vol tages, output cur ren ts, and ambient temperature of the system result in po wer di ssipation within the oper ati ng limits are met or if further thermal relief is required. 0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 2 .5 3 3 .5 4 4 .5 5 5 .5 6 ______ t a =+ 25 c , p d ( max ) = 0 .8 w - - - - t a =+ 85 c , p d ( max ) = 0 . 41 w vo = 3 .3 v inp ut vol tag e (v) maximum total output current (a) m a xim u m r e co m m e n d e d in p u t v o lta g e vo = 1.5 v fig ure 3 safe operating limit 0 0 .2 0 .4 0 .6 0 .8 1 1 .2 1 .4 1 .6 - 40 - 20 0 20 40 60 80 100 maximum power dissipation (w) amb ien t t emperat ure ( o c) t j ( max )= 150 c t j ( max )= 125 c fig ure 4 maximum p d vs . t a appl ications information (continued) the fo llowing procedure can be follo wed to de ter mine if the thermal design of the system is adequa te. th e junction tem perature of the sc560 can be determined in known operating conditions using the following equation: t j = t a +(p d x ja ) where t j = junction tem perature (c) t a = ambient temperature (c) p d = po wer dissipation ( w) ja = the rma l resistance junction to ambient (c/w) example an sc560d is used to pr ovi de outputs of 2.8v, 150ma from ldoa and 1.8v, 200ma from ldob. the in put voltage is 4.2v, and the ambient temperature of the system is 40c. p d = 0.15(4.2 C 2.8) + 0.2(4.2 C 1.8) = 0.69w and t j = 40 + (0.69 x 157) = 148.3c fig ures 3 and 4 show that the junction temperature wou ld be within the maximum speci ca tion of 150c for th is po wer di ssipation. thi s means that oper ati on of the sc560 under these conditions is within the speci ed limits and the device would not require further th ermal rel ief measures.
sc560 15 lay out consider ati ons whi le la you t for linear devices is generally not as critical as for a s witching application, careful attention to de tail will ensure rel iable oper ati on. the diag ram be low illustra tes proper la you t of a circuit using the sc560a. for variants that dont require current setting resistors, these devices can be omitted from the la you t. atta ch the part to a large copper footprin t, to enable better heat transfer from the device on pcbs where there are in ter nal po wer an d gro und planes. ? appl ications information (continued) pla ce the input, output, and bypass capacitors close to the device for optimal transient res ponse and device behavior. con nect all g rou nd connections directly to the gro und plane whenever possible to minimize gro und potential di erences on the pcb. ensure that the feedback resistors are placed as close as possible to the feedback pins. ?? ? r 1 r 2 r 3 r 4 c 4 c 3 c 2 c 1 1 u1 u 1 = sc 560 a
sc560 16 . 059 bsc 1. 50 bsc not es : . 004 8 . 000 . 018 - - (. 006 ) 0 . 10 8 . 024 . 002 0. 00 0 . 45 0. 05 0. 60 (0. 1524 ) - - . 004 0 . 10 1. 50 bsc 0. 40 bsc . 016 bsc . 014 0. 35 . 059 bsc cop lan ari ty appli es t o t he exposed pa d a s w ell as t he ter min als . 2. cont rol lin g d ime nsi ons ar e i n m illim eter s ( ang les in d egrees ). 1. inc hes dim ensi ons nom e bbb aaa a 1 a 2 dim n l e min d a mil lim eter s max min max nom pin 1 ind ica tor ( las er mar k ) b . 006 . 008 . 010 0. 15 0. 20 0. 25 d a e b a 1 aaa c a 2 c seati ng plan e e bxn lxn bbb c a b 1 2 n 0. 20 0 . 25 0. 17 0. 40 0. 30 0. 16 0. 12 a out line dr awi ng mlpq-ut8
sc560 17 lan d pattern mlpq-ut8 inc hes dim ensi ons p z xy c g dim mil lim eter s r . 004 0. 10 1. cont rol lin g d ime nsi ons ar e i n m illim eters ( ang les in d egr ees ). y x g z (g ) (z ) 2 x (c ) r p . 030 . 087 (. 057 ) . 028 0. 75 2. 20 (1. 45 ) 0. 70 0. 20 0. 40 . 016 . 008 thi s l and pa tter n i s f or ref eren ce pur poses onl y . cons ult yo ur m anu fac tur ing gr oup to en sur e yo ur com pany ' s m anu factur ing guide lin es ar e m et . not es : 2 .
sem tec h corporation pow er management products division 200 flynn road, camarillo, ca 93012 pho ne: (805) 498-2111 fax : (805) 498-3804 www .semtech.com con tact information sc560 18 ? sem tec h 2014 all rig hts re served. rep rod uction in whole or in part is prohibited without the prior written consent of the copyright own er. the in for mation presen ted in th is document does not form part of any quotation or contract, is belie ved to be accura te and reliable and may be changed without notic e. no liability will be ac cep ted by th e publisher for any con sequence of its use. publication thereof does not convey nor imply any license under pa ten t or other indust ria l or intellectual proper ty rig hts . semtech assumes no responsibility or liability whatsoever for an y failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual ph ysi cal or electrical stress including, but not limited t o, exp osure to parameters beyond the speci ed ma ximum r ati ngs or operation outside the speci ed range. semtech produc ts are not designed, intended, authorized or war ran ted to be suitable for use in li fe- support applications, devices or systems or other critical applic ati ons. inclusion of semtech products in such applic ati ons is understood to be under tak en solely at the customer s own risk. should a customer purchase or use semtech products for an y such unauthorized application, the customer shall indemnify and hold sem tec h and its o ce rs, employees, subsidiaries, a li ate s, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all ref erenced brands, product names, service names and trademarks are the property of their respective own ers.

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